ICS8735-21

700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR

IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR

7

ICS8735AM-21 REV. A JULY 31, 2008

AC Electrical Characteristics

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential

cross points.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions,

when the PLL is locked and the input reference frequency is stable.

NOTE 5: Characterized at VCO frequency of 622MHz.

NOTE 6: Phase jitter is dependent on the input source used.

Parameter

Symbol

Test Conditions

Minimum

Typical

Maximum

Units

Output Frequency

700

MHz

Propagation Delay; NOTE 1

PLL_SEL = 0V, f

≤ 700MHz

3.0

4.2

ns

tsk(o)

Output Skew; NOTE 2, 3

PLL_SEL = 0V

20

ps

tsk(Ø)

Static Phase Offset; NOTE 3, 4

PLL_SEL = 3.3V

-50

50

150

ps

tjit(cc)

Cycle-to-Cycle Jitter; NOTE 3, 5

25

ps

tjit(

θ)

Phase Jitter; NOTE 3, 5, 6

±50

ps

PLL Lock Time

1ms

Output Rise/Fall Time; NOTE 7

20% to 80% @ 50MHz

300

700

ps

odc

Output Duty Cycle

47

53

%