ATmega16 datasheet(69/357 Pages) ATMEL

69 / 357 page

2466S–AVR–05/09

ATmega16(L)

• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-

sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the

interrupt are defined in Table 35. The value on the INT0 pin is sampled before detecting edges.

If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate

an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is

selected, the low level must be held until the completion of the currently executing instruction to

generate an interrupt.

MCU Control and

Status Register –

MCUCSR

• Bit 6 – ISC2: Interrupt Sense Control 2

The Asynchronous External Interrupt 2 is activated by the external pin INT2 if the SREG I-bit and

the corresponding interrupt mask in GICR are set. If ISC2 is written to zero, a falling edge on

INT2 activates the interrupt. If ISC2 is written to one, a rising edge on INT2 activates the inter-

rupt. Edges on INT2 are registered asynchronously. Pulses on INT2 wider than the minimum

pulse width given in Table 36 will generate an interrupt. Shorter pulses are not guaranteed to

generate an interrupt. When changing the ISC2 bit, an interrupt can occur. Therefore, it is rec-

ommended to first disable INT2 by clearing its Interrupt Enable bit in the GICR Register. Then,

the ISC2 bit can be changed. Finally, the INT2 Interrupt Flag should be cleared by writing a logi-

cal one to its Interrupt Flag bit (INTF2) in the GIFR Register before the interrupt is re-enabled.

General Interrupt

Control Register –

GICR

• Bit 7 – INT1: External Interrupt Request 1 Enable

When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-

nal pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU

General Control Register (MCUCR) define whether the External Interrupt is activated on rising

Table 35. Interrupt 0 Sense Control

ISC01

ISC00

Description

The low level of INT0 generates an interrupt request.

Any logical change on INT0 generates an interrupt request.

The falling edge of INT0 generates an interrupt request.

The rising edge of INT0 generates an interrupt request.

Bit

765

432

JTD

ISC2

–

JTRF

WDRF

BORF

EXTRF

PORF

MCUCSR

Read/Write

R/W

Initial Value

See Bit Description

Table 36. Asynchronous External Interrupt Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Units

tINT

Minimum pulse width for

asynchronous external interrupt

Bit

654

INT1

INT0

INT2

–

IVSEL

IVCE

GICR

Read/Write

R/W

Initial Value

ATmega16 Scheda tecnica(PDF) 69 Page - ATMEL Corporation

ATmega16 Scheda tecnica(HTML) 69 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL