ATmega324P datasheet(311/377 Pages) ATMEL

311 / 377 page

311

7674F–AVR–09/09

ATmega164P/324P/644P

25.8

Serial Downloading

Both the Flash and EEPROM memory arrays can be programmed using a serial programming

bus while RESET is pulled to GND. The serial programming interface consists of pins SCK,

MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction

needs to be executed first before program/erase operations can be executed. NOTE, in Table

25-15 on page 311, the pin mapping for serial programming is listed. Not all packages use the

SPI pins dedicated for the internal Serial Peripheral Interface - SPI.

25.8.1

Serial Programming Pin Mapping

Figure 25-10. Serial Programming and Verify

(1)

Notes:

1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the

XTAL1 pin.

2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 2.7 - 5.5V

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming

operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase

instruction. The Chip Erase operation turns the content of every memory location in both the

Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods

for the serial clock (SCK) input are defined as follows:

Low: > 2 CPU clock cycles for f

ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

High: > 2 CPU clock cycles for f

ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

Table 25-15. Pin Mapping Serial Programming

Symbol

Pins

(PDIP-40)

Pins

(TQFP-44)

I/O

Description

MOSI

PB5

Serial Data in

MISO

PB6

Serial Data out

SCK

PB7

Serial Clock

VCC

GND

XTAL1

SCK

MISO

MOSI

RESET

+1.8 - 5.5V

AVCC

+1.8 - 5.5V

(2)

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