ATtiny261-ESMZ datasheet(71/227 Pages) ATMEL

71 / 227 page

7753C–AVR–07/09

ATtiny261/ATtiny461/ATtiny861

However, due to variation of the system clock frequency and duty cycle caused by Oscillator

source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum fre-

quency of an external clock source is less than f

clk_I/O/2.5.

An external clock source can not be prescaled.

Figure 13-2. Prescaler for Timer/Counter0

Note:

1. The synchronization logic on the input pins (

T0) is shown in Figure 13-1.

13.1

13.1.1

TCCR0B – Timer/Counter0 Control Register B

• Bit 4 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the

value that is written to the PSR0 bit is kept, hence keeping the Prescaler Reset signal asserted.

This ensures that the Timer/Counter is halted and can be configured without the risk of advanc-

ing during configuration. When the TSM bit is written to zero, the PSR0 bit is cleared by

hardware, and the Timer/Counter start counting.

• Bit 3 – PSR0: Prescaler Reset Timer/Counter0

When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared

immediately by hardware, except if the TSM bit is set.

• Bits 2, 1, 0 – CS02, CS01, CS00: Clock Select0, Bit 2, 1, and 0

The Clock Select0 bits 2, 1, and 0 define the prescaling source of Timer0.

PSR0

Clear

clk

I/O

Synchronization

Bit

76543

210

0x33 (0x53)

TSM

PSR0

CS02

CS01

TCCR0B

Read/Write

R/W

Initial Value

00000

000

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