R5F363AMDFB datasheet(95/115 Pages) RENESAS

95 / 115 page

REJ03B0271-0100 Rev.1.00 Sep 15, 2009

Page 95 of 113

M16C/63 Group

5. Electrical Characteristics

Figure 5.29

Timing Diagram

BCLK

CSi

ADi

ALE

30ns(max.)

0ns(min.)

Hi-Z

DBi

0ns(min.)

BHE

Read timing

50ns(min.)

Memory Expansion Mode and Microprocessor Mode

(in no wait state setting)

WR, WRL,

WRH

30ns(max.)

0ns(min.)

BCLK

CSi

ADi

ALE

BHE

0ns(min.)

DBi

Write timing

Hi-Z

f(BCLK)

= V

= 3 V

CC1

CC2

25ns(max.)

th(BCLK-CS)

tcyc

th(BCLK-AD)

0ns(min.)

td(BCLK-AD)

td(BCLK-ALE)

-4ns(min.)

th(RD-AD)

0ns(min.)

td(BCLK-RD)

th(BCLK-RD)

0ns(min.)

tac1(RD-DB)

(0.5

× t

-60)ns(max.)

cyc

tsu(DB-RD)

th(RD-DB)

th(BCLK-ALE)

30ns(max.)

td(BCLK-CS)

30ns(max.)

td(BCLK-CS)

30ns(max.)

0ns(min.)

th(BCLK-CS)

tcyc

30ns(max.)

0ns(min.)

25ns(max.)

td(BCLK-ALE)

-4ns(min.)

th(BCLK-ALE)

td(BCLK-AD)

th(BCLK-AD)

th(WR-AD)

(0.5

× t

-10)ns(min.)

cyc

td(BCLK-WR)

th(BCLK-WR)

td(BCLK-DB)

th(BCLK-DB)

td(DB-WR)

(0.5

× t

-40)ns(min.)

cyc

th(WR-DB)

(0.5

× t

-10)ns(min.)

cyc

40ns(max.)

Measuring conditions

= V

= 3 V

CC1

CC2

Input timing voltage: V = 0.6 V, V

= 2.4 V

Output timing voltage: V

= 1.5 V, V

= 1.5 V

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