R5F363AMDFB datasheet(103/115 Pages) RENESAS

103 / 115 page

REJ03B0271-0100 Rev.1.00 Sep 15, 2009

Page 103 of 113

M16C/63 Group

5. Electrical Characteristics

Figure 5.33

Timing Diagram

Read timing

Write timing

BCLK

CSi

ALE

DBi

ADi

BHE

WR, WRL

WRH

BCLK

CSi

ALE

DBi

ADi

BHE

tcyc

td(BCLK-CS)

30ns(max.)

Hi-Z

tsu(DB-RD)

50ns(min.)

Hi-Z

= V

= 3 V

CC1

CC2

Memory Expansion Mode and Microprocessor Mode

(in wait state setting 2

φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and

when inserting 1 to 3 recovery cycles and accessing external area)

n: 3 (when 2

φ + 3φ)

4 (when 2

φ + 4φ or 3φ + 4φ)

5 (when 4

φ + 5φ)

th(BCLK-CS)

0ns(min.)

td(BCLK-AD)

30ns(max.)

th(BCLK-AD)

0ns(min.)

td(BCLK-ALE)

25ns(max.)

th(BCLK-ALE)

-4ns(min.)

td(BCLK-RD)

30ns(max.)

th(BCLK-RD)

0ns(min.)

th(RD-DB)

0ns(min.)

tcyc

td(BCLK-CS)

30ns(max.)

td(BCLK-AD)

30ns(max.)

th(BCLK-ALE)

-4ns(min.)

td(BCLK-ALE)

25ns(max.)

td(BCLK-WR)

30ns(max.)

td(BCLK-DB)

40ns(max.)

th(BCLK-CS)

0ns(min.)

th(BCLK-AD)

0ns(min.)

th(WR-AD)

(m × t

-10)ns(min.)

cyc

th(BCLK-WR)

0ns(min.)

th(BCLK-DB)

0ns(min.)

th(WR-DB)

(m × t

-10)ns(min.)

cyc

(n × t

-60)ns(max.)

cyc

tac4(RD-DB)

(n × t

-40)ns(min.)

cyc

td(DB-WR)

tcyc =

m: 1 (when 1 recovery cycle inserted )

2 (when 2 recovery cycles inserted)

3 (when 3 recovery cycles inserted)

Measuring conditions

= V

= 3 V

CC1

CC2

Input timing voltage: V = 0.6 V, V

= 2.4 V

Output timing voltage: V

= 1.5 V, V

= 1.5 V

th(RD-AD)

(m × t

+0)ns(min.)

cyc

f(BCLK)

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