ATtiny5 datasheet(18/168 Pages) ATMEL

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8127C–AVR–10/09

ATtiny4/5/9/10

6.1.4

ADC Clock – clkADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks

in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion

results.

The ADC is available in ATtiny5/10, only.

6.2

Clock Sources

All synchronous clock signals are derived from the main clock. The device has three alternative

sources for the main clock, as follows:

• Calibrated Internal 8 MHz Oscillator (see page 18)

• External Clock (see page 18)

• Internal 128 kHz Oscillator (see page 19)

See Table 6-3 on page 21 on how to select and change the active clock source.

6.2.1

Calibrated Internal 8 MHz Oscillator

The calibrated internal oscillator provides an approximately 8 MHz clock signal. Though voltage

and temperature dependent, this clock can be very accurately calibrated by the user. See Table

16-2 on page 118, Figure 17-39 on page 142 and Figure 17-40 on page 142 for more details.

This clock may be selected as the main clock by setting the Clock Main Select bits CLKMS[1:0]

in CLKMSR to 0b00. Once enabled, the oscillator will operate with no external components. Dur-

ing reset, hardware loads the calibration byte into the OSCCAL register and thereby

automatically calibrates the oscillator. The accuracy of this calibration is shown as Factory cali-

bration in Table 16-2 on page 118.

When this oscillator is used as the main clock, the watchdog oscillator will still be used for the

watchdog timer and reset time-out. For more information on the pre-programmed calibration

value, see section “Calibration Section” on page 110.

6.2.2

External Clock

To use the device with an external clock source, CLKI should be driven as shown in Figure 6-2.

The external clock is selected as the main clock by setting CLKMS[1:0] bits in CLKMSR to 0b10.

Figure 6-2.

External Clock Drive Configuration

When applying an external clock, it is required to avoid sudden changes in the applied clock fre-

quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from

one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the

MCU is kept in reset during such changes in the clock frequency.

EXTERNAL

CLOCK

SIGNAL

CLKI

GND

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