TAS5613

SLAS676 – NOVEMBER 2009

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Note T1: PVDD decoupling bulk capacitors C60-C64 should be as close as possible to the PVDD and GND_X pins,

the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and

without going through vias. No vias or traces should be blocking the current path.

Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and

close to the pins.

Note T3: Heat sink needs to have a good connection to PCB ground.

Note T4: Output filter capacitors must be linear in the applied voltage range preferable metal film types.

Figure 14. Printed Circuit Board - Top Layer

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