AD5541ABCPZ datasheet(5/24 Pages) AD

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Preliminary Technical Data

AD5541A/AD5542A/AD5512AA

Rev. P

rA | Page 5 of 24

Parameter

Min

Typ

Max

Unit

Test Condition

POWER REQUIREMENTS

VDD

2.7

5.5

IDD

200

TBD

µA

VLOGIC

1.8

5.5

ILOGIC

200

TBD

µA

Power Dissipation

1.5

TBD

1 Reference input resistance is code-dependent, minimum at 0x8555.

2 Guaranteed by design, not subject to production test.

TIMING CHARACTERISTICS

VLOGIC = 1.8 V to 5.5 V V, VDD = 5V, VREF = 2.5 V, VINH = 90% of VLOGIC, VINL = 10% of VLOGIC, AGND = DGND = 0 V; −40°C < TA < +105°C,

unless otherwise noted.

Table 2.

Parameter1, 2

Limit

Unit

Description

fSCLK

MHz max

SCLK cycle frequency

ns min

SCLK cycle time

ns min

SCLK high time

ns min

SCLK low time

ns min

CS low to SCLK high setup

ns min

CS high to SCLK high setup

ns min

SCLK high to CS low hold time

ns min

SCLK high to CS high hold time

ns min

Data setup time

ns min

Data hold time (VINH = 90% of VDD, VINL = 10% of VDD)

ns min

Data hold time (VINH = 3V, VINL = 0 V)

t10

ns min

LDAC pulsewidth

t11

ns min

CS high to LDAC low setup

t12

ns min

CS high time between active periods

t13

ns min

CLR pulsewidth

1 Guaranteed by design and characterization. Not production tested

2 All input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VINL + VINH)/2.

Figure 5. Timing Diagram

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