ADE7858ACPZ-REF datasheet(53/76 Pages) AD

53 / 76 page

Preliminary Technical Data

ADE7858

Rev. PrA | Page 53 of 76

ADE7858 samples data on the low to high transitions of SCLK.

The most significant 7 bits of the address byte can have any

value, but as a good programming practice, they should be

different from b#0111000, the 7 bits used in the I2C protocol.

Bit 0 (READ/ WRITE ) of the address byte must be 1 for a read

operation. Next, the master sends the 16-bit address of the

address of the register on a low-to-high transition of SCLK, it

begins to transmit its content on the MISO line when the next

SCLK high-to-low transition occurs, so the master can sample

the data on low to high SCLK transition. After the master

receives the last bit, it sets SS and SCLK lines high and the

communication ends. The data lines MOSI and MISO go in

high impedance state.

See Figure 63 for details of the SPI read operation.

15 14

Reg Address

31 30

SCLK

MOSI

MISO

Figure 63. SPI read operation of a 32-bit register

15 14

Reg Address

31 30

SCLK

MOSI

Figure 64. SPI Write operation of a 32-bit register

SPI Write Operation

The write operation using the SPI interface of the ADE7858

initiates when the master sets SS pin low and begins sending

one byte representing the address of the ADE7858 on the

MOSI line. The master sets data on the MOSI line starting with

the first high to low transition of SCLK. The SPI of the

ADE7858 samples data on the low to high transitions of SCLK.

The most significant 7 bits of the address byte can have any

value, but as a good programming practice, they should be

different from b#0111000, the 7 bits used in the I2C protocol.

Bit 0 (READ/ WRITE ) of the address byte must be 0 for a write

operation. Next, the master sends the 16-bit address of the

transmitted, the master sets SS and SCLK lines high at the end

of SCLK cycle and the communication ends. The data lines

MOSI and MISO go in high impedance state.

See Figure 64 for details of the SPI write operation.

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