HT46R01B datasheet(49/71 Pages) HOLTEK

49 / 71 page

HT46R01B/02B/01N/02N

HT48R01B/02B/01N/02N

Rev.1.00

December 15, 2009

Interrupts

Interrupts are an important part of any microcontroller

system. When an external event or an internal function

such as a Timer/Event Counter or Time Base requires

microcontroller attention, their corresponding interrupt

will enforce a temporary suspension of the main pro-

gram allowing the microcontroller to direct attention to

their respective needs.

The devices contain a single external interrupt and mul-

tiple internal interrupts. The external interrupt is con-

trolled by the action of the external interrupt pin, while

the internal interrupt is controlled by the Timer/Event

Counters and Time Base overflows.

Interrupt Register

Overall interrupt control, which means interrupt enabling

and request flag setting, is controlled by using two regis-

ters, INTC0 and INTC1. By controlling the appropriate

enable bits in this registers each individual interrupt can

be enabled or disabled. Also when an interrupt occurs,

the corresponding request flag will be set by the

microcontroller. The global enable flag if cleared to zero

will disable all interrupts.

Interrupt Operation

A Timer/Event Counter overflow, a Time Base event or

an active edge on the external interrupt pin will all gener-

ate an interrupt request by setting their corresponding

request flag, if their appropriate interrupt enable bit is

set. When this happens, the Program Counter, which

stores the address of the next instruction to be exe-

cuted, will be transferred onto the stack. The Program

Counter will then be loaded with a new address which

will be the value of the corresponding interrupt vector.

The microcontroller will then fetch its next instruction

from this interrupt vector. The instruction at this vector

will usually be a JMP statement which will jump to an-

other section of program which is known as the interrupt

service routine. Here is located the code to control the

appropriate interrupt. The interrupt service routine must

be terminated with a RETI instruction, which retrieves

the original Program Counter address from the stack

and allows the microcontroller to continue with normal

execution at the point where the interrupt occurred.

The various interrupt enable bits, together with their as-

sociated request flags, are shown in the following dia-

gram with their order of priority.

Once an interrupt subroutine is serviced, all the other in-

terrupts will be blocked, as the EMI bit will be cleared au-

tomatically. This will prevent any further interrupt nesting

from occurring. However, if other interrupt requests oc-

cur during this interval, although the interrupt will not be

immediately serviced, the request flag will still be re-

corded. If an interrupt requires immediate servicing

while the program is already in another interrupt service

routine, the EMI bit should be set after entering the rou-

tine, to allow interrupt nesting. If the stack is full, the in-

terrupt request will not be acknowledged, even if the

related interrupt is enabled, until the Stack Pointer is

decremented. If immediate service is desired, the stack

must be prevented from becoming full.

A u t o m a t i c a l l y C l e a r e d b y I S R

M a n u a l l y S e t o r C l e a r e d b y S o f t w a r e

E x t e r n a l I n t e r r u p t

R e q u e s t F l a g I N T F

T i m e r / E v e n t C o u n t e r 0

I n t e r r u p t R e q u e s t F l a g T 0 F

I N T E

T 0 E

E M I

P r i o r i t y

H i g h

L o w

I n t e r r u p t

P o l l i n g

A D E

T 1 E

T i m e r / E v e n t C o u n t e r 1

I n t e r r u p t R e q u e s t F l a g T 1 F

A / D C o n v e r s i o n

I n t e r r u p t R e q u e s t F l a g A D F

T B E

T i m e B a s e

I n t e r r u p t R e q u e s t F l a g T B F

E M I

A u t o m a t i c a l l y D i s a b l e d w h e n i n t e r r u p t

e v e n t i s s e r v i c e d E n a b l e d m a n u a l l y o r

a u t o m a t i c a l l y w i t h R E T I i n s t r u c t i o n

E M I

Note: HT48R01B/HT48R02B/HT48R01N/HT48R02N haven

¢t ADC interrupt

Interrupt Scheme

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