HT83F20P datasheet(21/61 Pages) HOLTEK

21 / 61 page

HT83FXX

Rev. 1.00

May 12, 2009

reload the value already loaded into the preload register

and continue counting. The interrupt can be disabled by

ensuring that the Timer Interrupt Enable bit in the Inter-

rupt Control Register, INTC, is reset to zero.

Prescaler

All of the 8-bit timers possess a prescaler. Bits 0~2 of

their associated timer control register, define the

pre-scaling stages of the internal clock source of the

Timer. The Timer overflow signal can be used to gener-

ate signals for the Timer interrupt.

Programming Considerations

The internal system clock is used as the timer clock

source and is therefore synchronized with the overall

operation of the microcontroller. In this mode, when the

appropriate timer register is full, the microcontroller will

generate an internal interrupt signal directing the pro-

gram flow to the respective internal interrupt vector.

When the Timer is read, the clock is blocked to avoid er-

rors, however as this may result in a counting error, this

should be taken into account by the programmer. Care

must be taken to ensure that the timers are properly ini-

tialized before using them for the first time. The associ-

ated timer enable bits in the interrupt control register must

be properly set otherwise the internal interrupt associated

with the timer will remain inactive. The edge select, timer

mode and clock source control bits in timer control regis-

ter must also be correctly set to ensure the timer is prop-

erly configured for the required application. It is also

important to ensure that an initial value is first loaded into

the timer registers before the timer is switched on; this is

because after power-on the initial values of the timer reg-

isters are unknown. After the timer has been initialized

the timer can be turned on and off by controlling the en-

able bit in the timer control register.

b 7

T O N

T M 0

T M 1

b 0

N o t i m p l e m e n t e d , r e a d a s " 0 "

T i m e r C o u n t i n g E n a b l e

1 : e n a b l e

0 : d i s a b l e

O p e r a t i n g M o d e S e l e c t

T 0 T M 1

T 1 T M 1

T 0 T M 0

T 1 T M 0

n o m o d e a v a i l a b l e

t i m e r m o d e

n o m o d e a v a i l a b l e

T M R 0 C / T M R 1 C R e g i s t e r

N o t i m p l e m e n t e d , r e a d a s " d o n ' t c a r e "

P S C 2

P S C 1

P S C 0

T i m e r P r e s c a l e r R a t e S e l e c t

T 0 P S C 2

T 1 P S C 2

T 0 P S C 1

T 1 P S C 1

T 0 P S C 0

T 1 P S C 0

T i m e r R a t e

1 : 2

1 : 4

1 : 8

1 : 1 6

1 : 3 2

1 : 6 4

1 : 1 2 8

1 : 2 5 6

Timer Control Register

I n c r e m e n t

T i m e r C o n t r o l l e r

P r e s c a l e r O u t p u t

T i m e r + 1

T i m e r + 2

T i m e r + N

T i m e r + N + 1

Timer Mode Timing Diagram

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