PCF2129AT datasheet(21/68 Pages) NXP

Il numero della parte	PCF2129AT

Spiegazioni elettronici	Integrated RTC, TCXO and quartz crystal

PDF	68 Pages

Scroll/Zoom	100%

Produttore elettronici	NXP [NXP Semiconductors]

Homepage	http://www.nxp.com

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21 / 68 page

PCF2129A_1

Product data sheet

Rev. 01 — 13 January 2010

21 of 68

NXP Semiconductors

PCF2129A

Integrated RTC, TCXO and quartz crystal

The setting of the PORO mode requires that POR_OVRD in register Control_1 is set logic

1 and that the signals at the interface pins SDA/CE and SCL are toggled as illustrated in

Figure 12. All timings shown are required minimums.

Once the override mode is entered, the device is immediately released from the reset

state and the set-up operation can commence.

The PORO mode is cleared by writing logic 0 to POR_OVRD. POR_OVRD must be

logic 1 before a re-entry into the override mode is possible. Setting POR_OVRD logic 0

during normal operation has no effect except to prevent accidental entry into the PORO

mode.

Fig 12. Power-On Reset Override (PORO) sequence, valid for both I2C-bus and SPI-bus

001aaj326

minimum 2000 ns

minimum 500 ns

8 ms

power up

SCL

reset override

SDA/CE

PCF2129AT Scheda tecnica(PDF) 21 Page - NXP Semiconductors