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AS1538 Scheda tecnica(PDF) 15 Page - ams AG

Il numero della parte AS1538
Spiegazioni elettronici  8/4-Channel, 12-Bit I2C Analog-to-Digital Converter
PDF  20 Pages
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Produttore elettronici  AMSCO [ams AG]
Homepage  http://www.ams.com
Logo AMSCO - ams AG

AS1538 Scheda tecnica(HTML) 15 Page - ams AG

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Revision 1.03
15 - 20
AS1538/AS1540
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
Reading with Internal Reference On/Off
The internal reference defaults to off when the AS1538/AS1540 power is on. If the reference (internal or external) is
continuously turned on and off, a proper amount of settling time must be added before a normal conversion cycle can
be started. The exact amount of settling time needed varies depending on the reference capacitor. For example for a
reference capacitor of 4.7µF and considering the output impedance of the internal reference of 30
Ω and the amount of
time to fully charge the capacitor will be 1.4ms. If the reference capacitor is not fully discharged this time can be
reduced greatly.
Figure 29 shows the correct internal reference enable sequence before issuing the typical read sequences required for
the mode when an internal reference is used.
Note: Typical read sequences can be re-used once the internal reference has settled.
Figure 29. Internal Reference Enable Sequence and Typical Read Sequence
Where:
A: Acknowledge (SDA Low)
N: Not Acknowledge (SDA High)
S: START Condition
P: STOP Condition
Sr: Repeated START Condition
W: 0 (Write)
R: 1 (Read)
X: Dont Care
S
1
0
0
1
0
A1
A0
W
X
X
X
X
1
X
X
X
A
A
Write-Addressing Byte
Command Byte
Internal-Reference Enable Sequence
P
Wait until required settling time reached
From Master to Slave
From Slave to Master
Internal-Reference
Enable Settling Time
Sr
1
0
0
1
0
A1
A0
W
SD
C2
C1
C0
1
PD0
X
X
A
A
Write-Addressing Byte
Command Byte
ADC Powerdown Mode
ADC Sampling Mode
0
0
0
0
D11 D10 D9
D8
D7
A
D0
N
P
D6 ... D1
Sr
1
0
0
1
0
A1
A0
R
A
ADC Conversion Mode
ADC Powerdown Mode *
Read-Addressing Byte
2 x (8-bits +ACK/NACK
Settled Internal Reference
Typical Mode Read Sequence
**
* Dependant on powerdown selection
bits PD0 and PD1.
** To remain in HS mode, use repeated
STARTs instead of STOPs
Settled Internal Reference



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