AS2702 – AS-Interface Slave IC

Revision 1.3, 21-Aug-08

Page 9 of 13

Symbol

Parameter

Min

Max

Unit Note

VSCHLT

Input threshold voltage

2.5

3.5

V

2

VIN

Acceptable input voltage @ output off

-0.3

40

V

Notes:

1

The passive high-side current-source provides an about constant input current @ 0V <= VIN <= 4V

2

No hysteresis implemented

Though equipped for bidirectional data transfer as D3, …, D0, the parameter port is nevertheless less flexible than the data port.

Note the following differences:

a)

The parameter port is set portwise, the data port bitwise by the IO-configuration code;

b)

The parameter port can only be set to either ‘output’ or ‘input’. A bidirectional behaviour within a strobe cycle is not possible;

c)

The parameter port is set to ‘output’ as a rule; the only exception occurs in case of IO-configuration 7 and a master data

request, which set it to ‘input’.

To govern the data transfer at the parameter port P3, …, P0 strobe pin PSTBn is equipped with a low-side open-drain output switch

plus a passive high-side current source with a nom. 10µA pull-up current capability. Typically the PSTBn-strobe width is about 6µs

see Figure 4. (However to simplify and shorten the component test time of the slave device, the PSTBn pin is also used as an input.

Input low pulses of more than 50µs each will step and cycle the device through 3 different test modes beyond the regular operation

as described in this datasheet.)

The dc- and timing parameters of strobe pin PSTBn are specified as follows:

Symbol

Parameter

Min

Max

Unit Note

IOUTLO

Sink current @ output L

10

mA VOUT = 1V

IOUTHI

Leakage current @ output off

-10

10

µA

VOUT = 5V

IINLO

Input current @ VIN = 1V

-5

-20

µA

1

VSCHLT

Input threshold voltage

1.5

3.5

V

2

VIN

Acceptable input voltage @ output off

-0.3

40

V

tNOTM

PSTBn L-phase width, not triggering test mode

35

µs

tTM

PSTBn L-phase width, triggering test mode

50

µs

CPINEXT

Stray capacitance

20

pF

Notes:

1

PSTBn is equipped with an on-chip pull-up current source, which ensures a sufficiently fast LH-edge upon output switch-off in

open-pin condition, to prevent erroneous test mode triggering.

If PSTBn has an external load connected to it, an additional external pull-up resistor may be needed to prevent erroneous test

mode triggering upon output switch-off

2

No hysteresis implemented