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TTTech Computertechnik AG

Revision 2.1

12 - 20

AS8202NF TTP-C2NF

Figure 4. Write Access Timing (CEB Controlled)

Figure 5. Write Access Timing (WEB Controlled)

Figure 6. Read Access Timing (CEB Controlled)

Figure 7. Read Access Timing (OEB Controlled)

Synchronous READYB Generation

Figure 8. Synchronous READYB Timing

Synchronous READYB is aligned to host clock (with pulse duration of one host clock cycle) to fulfill the required host

timing constraints for input setup and input hold time to/after host clock rising edge.

mode of operation. Due to possible metastability occurrence, it is not recommended to be used in safety critical

systems.

CEB

WEB

A

Valid

Valid

D

OEB

READYB

1a

1b

2a

2b

3

6

5

4

CEB

WEB

A

Valid

Valid

D

OEB

READYB

1a

1b

2a

2b

6

5

3

4

CEB

WEB

A

Valid

D

OEB

READYB

7a

7b

8

11c

10

9

12

Invalid

Valid

11a

11b

CEB

WEB

A

Valid

D

OEB

READYB

7a

7b

8

11c

10

9

12

Invalid

Valid

11a

11b

asynchronous READYB

RAM_CLK_TESTSE

synchronous READYB

13

14

15