DSPIC33FJ32GS406 datasheet(4/416 Pages) MICROCHIP

4 / 416 page

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

DS70591B-page 4

Preliminary

 2009 Microchip Technology Inc.

Peripheral Features (Continued)

• UART (up to two modules):

- Interrupt on address bit detect

- Interrupt on UART error

- Wake-up on Start bit from Sleep mode

- 4-character TX and RX FIFO buffers

- LIN bus support

-IrDA© encoding and decoding in hardware

- High-Speed Baud mode

- Hardware Flow Control with CTS and RTS

• Enhanced CAN (ECAN™ module) 2.0B active:

- Up to eight transmit and up to 32 receive buffers

- 16 receive filters and three masks

- Loopback, Listen Only and Listen All

- Messages modes for diagnostics and bus

monitoring

- Wake-up on CAN message

- Automatic processing of Remote

Transmission Requests

- FIFO mode using DMA

- DeviceNet™ addressing support

• Quadrature Encoder Interface (up to 2 modules):

- Phase A, Phase B, and index pulse input

- 16-bit up/down position counter

- Count direction status

- Position Measurement (x2 and x4) mode

- Programmable digital noise filters on inputs

- Alternate 16-bit Timer/Counter mode

- Interrupt on position counter rollover/underflow

High-Speed PWM Module Features:

• Up to nine PWM generators with up to 18 outputs

• Primary and Secondary time-base

• Individual time base and duty cycle for each of the

PWM output

• Dead time for rising and falling edges:

- Duty cycle resolution of 1.04 ns

- Dead-time resolution of 1.04 ns

• Phase shift resolution of 1.04 ns

• Frequency resolution of 1.04 ns

• PWM modes supported:

- Standard Edge-Aligned

- True Independent Output

- Complementary

- Center-Aligned

- Push-Pull

-Multi-Phase

- Variable Phase

- Fixed Off-Time

- Current Reset

- Current-Limit

• Independent Fault/Current-Limit inputs

• Output override control

• Special Event Trigger

• PWM capture feature

• Prescaler for input clock

• Dual Trigger from PWM TO ADC

• PWMxL, PWMxH output pin swapping

• On-the-Fly PWM Frequency, Duty cycle and

Phase Shift changes

• Disabling of Individual PWM generators

• Leading-Edge Blanking (LEB) functionality

High-Speed Analog Comparator:

• Up to four Analog Comparators:

- 20 ns response time

- 10-bit DAC for each analog comparator

- DACOUT pin to provide DAC output

- Programmable output polarity

- Selectable input source

- ADC sample and convert capability

• PWM module interface:

- PWM Duty Cycle Control

- PWM Period Control

- PWM Fault Detect

Interrupt Controller:

• 5-cycle latency

• Up to five external interrupts

• Seven programmable priority levels

• Five processor exceptions

High-Speed 10-bit ADC:

• 10-bit resolution

• Up to 24 input channels grouped into 12

conversion pairs

• Two internal reference monitoring inputs grouped

into a pair

• Successive Approximation Register (SAR)

converters for parallel conversions of analog pairs:

- 4 Msps for devices with two SARs

- 2 Msps for devices with one SAR

• Dedicated result buffer for each analog channel

• Independent trigger source section for each

analog input conversion pairs

Power Management:

• On-chip 2.5V voltage regulator

• Switch between clock sources in real time

• Idle, Sleep, and Doze modes with fast wake-up

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