TS4GDOM40V datasheet(40/52 Pages) TRANSCEND

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Transcend Information Inc.

Ver 1.7

Device Terminating an Ultra DMA Data-In Burst

The device terminates an Ultra DMA Data-In burst by following the steps lettered below. The timing

diagram is shown in below: Ultra DMA Data-In Burst Device Termination Timing. The timing parameters

are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13:

Ultra DMA Data Burst Timing Descriptions.

The following steps shall occur in the order they are listed unless otherwise specifically allowed:

(a) The device shall not pause an Ultra DMA data burst until at least one data word of an Ultra DMA data

burst has been transferred.

(b) The device shall pause an Ultra DMA data burst by not generating DSTROBE edges.

− The host shall not immediately assert STOP to initiate Ultra DMA data burst termination

when the device stops generating STROBE edges. If the device does not negate DMARQ, in order to

initiate Ultra DMA data burst termination, the host shall negate -HDMARDY and wait tRP before

asserting STOP.

(d) The device shall resume an Ultra DMA data burst by generating a DSTROBE edge.

ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH.

NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM.

Notes: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ

and DMACK are negated. A[02:00], -CS0 & -CS1 are True IDE mode signal definitions.

TS4GDOM40V Scheda tecnica(PDF) 40 Page - Transcend Information. Inc.