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STTS2002B2DN3F Scheda tecnica(PDF) 3 Page - STMicroelectronics |
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STTS2002B2DN3F Scheda tecnica(HTML) 3 Page - STMicroelectronics |
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3 / 9 page ![]() STTS2002 Description Doc ID 17216 Rev 1 3/9 Figure 1. Logic diagram 1. SDA and EVENT are open drain. Figure 2. TDFN8 connections (top view) 1. SDA and EVENT are open drain. Table 1. Signal names Pin Symbol Description Direction 1 A0 Serial bus address selection pin. Can be tied to VSS or VDD. Input 2 A1 Serial bus address selection pin. Can be tied to VSS or VDD. Input 3 A2 Serial bus address selection pin. Can be tied to VSS or VDD. Input 4VSS Supply ground 5SDA(1) 1. SDA and EVENT are open drain. Serial data Input/output 6 SCL Serial clock Input 7 EVENT(1) Event output pin. Open drain and active-low. Output 8VDD Supply power (2.3 V to 3.6 V) AI12261 SDA(1) VDD STTS2002 VSS SCL EVENT(1) A 2 A 1 A 0 1 SDA(1) GND SCL EVENT(1) A1 A0 VDD A2 AI12262 2 3 4 8 7 6 5 |
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