PAS6311LT Specification

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2

PixArt Imaging Inc.

v1.5 2007/10/02

1.

Pin Assignment

PX0

PX1

PX7

PX9

VDDQ

PX4

PX5

PX6

PX8

VDDA

PX3

PX2

VSSA

VDDAY

VSSD

VDDD

VSYNC

CSB

SYSCLK

HSYNC

SCL

SDA

PAS6311LT

-- Top View --

A1

A2

A3

A4

A5

B1

B2

B3

B4

B5

C1

C2

C4

C5

D1

D2

D4

D5

E1

E2

E3

E4

E5

RESET

D3

PXCLK

Figure 1.1 Shows the PAS6311LT pin diagram

Pin No.

Name

Type

Description

C4

VSSA

GND

Analog ground.

B5

VDDA

PWR

Analog VDD, 2.5V.

D5

CSB

IN

Power Down (chip power down if high ).

C5

VDDAY

IN

Internal voltage reference.

D2

VDDD

PWR

Digital core VDD, 1.8V.

D4

VSYNC

OUT

Vertical synchronization signal.

E3

HSYNC

OUT

Horizontal synchronization signal.

D3

PXCLK

OUT

Pixel clock output.

A5

VDDQ

PWR

I/O VDD, 1.8V ~ 3.3V.

E2

SYSCLK

IN

Master clock input.

E1

RESET

IN

Resets all registers to default ( chip reset if high .)

D1

VSSD

GND

Digital ground.

A4

PX9

OUT

Digital data out.

B4

PX8

OUT

Digital data out.

A3

PX7

OUT

Digital data out.

B3

PX6

OUT

Digital data out.

B2

PX5

OUT

Digital data out.

B1

PX4

OUT

Digital data out.

C1

PX3

OUT

Digital data out.

C2

PX2

OUT

Digital data out.

A2

PX1

OUT

Digital data out.

A1

PX0

OUT

Digital data out.

E4

SCL

IN

I2C clock.

E5

SDA

I/O

I2C data. Internal pull high resister is 10KΩ.