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VG37648041AT Scheda tecnica(PDF) 6 Page - Vanguard International Semiconductor |
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VG37648041AT Scheda tecnica(HTML) 6 Page - Vanguard International Semiconductor |
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6 / 86 page ![]() Document : 1G5-0157 Rev.1 Page 6 VIS Preliminary VG37648041AT 256M:x4, x8, x16 CMOS Synchronous Dynamic RAM COLUMN DECODER (x32) FUNCTIONAL BLOCK DIAGRAM- X16 CONFIGURATION CKE CLK# Generator CLK CS# WE# CAS# RAS# LOGIC MODE REGISTERS REFRESH COUNTER 13 ROW- ADDRESS MUX BANK0 ROW- ADDRESS LATCH & DECODER 8192 BANK0 MEMORY ARRAY SENSE AMPLIFIERS BANK0 MEMORY ARRAY (8192x256x32) SENSE AMPLIFIERS BANK1 BANK2 BANK3 13 I/O GATING DM MASK LOGIC BANK0 COLUMN ADDRESS CONTROL LOGIC COUNTER/ LATCH 8 COL0 ADDRESS RESGISTER 15 A0-A12 BA0-BA1 2 9 13 13 2 READ LATCH MUX 32 WRITE FIFO & DRIVERS 32 32 16 16 ctk out in ctk CLK DQS GENERATOR DRVRS DLL CLK 1 DQS COL0 16 2 32 MASK DATA 1 1 16 16 1 1 16 16 1 16 RCVRS COL0 DO0- DQ15,LDM LDQS, 1 1 Note 1: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not necessarily represent an actual circuit implementation. Note 2: LDM and VDM are unidirectional signal (input only) but is internally loaded to match the load of the bidirectional DQ and DQS signals. INPUT REGISTERS UDM UDQS DATA |
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