WM2616CD datasheet(5/9 Pages) WOLFSON

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Production Data Rev 1.0

WM2616

WOLFSON MICROELECTRONICS LTD

Production Data Rev 1.0 June 1999

SERIAL INTERFACE

SUC16FS

SUFS

SCLK

DIN

NCS

D12

D13

D14

D15

SUD

SUCSFS

WHFS

SUC16CS

Figure 1 Timing Diagram

Test Conditions:

RL = 10k

Ω, C

L = 100pF. VDD = 5V

±± 10%, V

REF = 2.048V and VDD = 3V

±± 10%, V

REF = 1.024V over recommended operating free-air

temperature range (unless noted otherwise).

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tSUCSFS

Setup time NCS low before negative FS edge.

tSUFS

Setup time FS low before first negative SCLK edge.

tSUC16FS

Setup time, sixteenth negative SCLK edge after FS low

on which D0 is sampled before rising edge of FS.

tSUC16CS

Setup time, sixteenth positive SCLK edge (first positive

after D0 sampled) before NCS rising edge. If FS is used

instead of the sixteenth positive edge to update the DAC,

then the setup time is between the FS rising edge and

the NCS rising edge.

tWH

Pulse duration, SCLK high.

tWL

Pulse duration, SCLK low.

tSUD

Setup time, data ready before SCLK falling edge.

tHD

Hold time, data held valid after SCLK falling edge.

tWHFS

Pulse duration, FS high.

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