WM8192 datasheet(21/24 Pages) WOLFSON

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WM8192

WOLFSON MICROELECTRONICS LTD

PP Rev 1.0 June 2000

BIT

NAME(S)

DEFAULT

DESCRIPTION

Determines the output data format.

1MUXOP

0 = 8-bit multiplexed (8+8 bits)

1 = 4-bit multiplexed mode (4+4+4+4-bits)

2INVOP

Digitally inverts the polarity of output data.

0 = negative going video gives negative going output,

1 = negative-going video gives positive going output data.

VRLCEXT

When set powers down the RLCDAC, changing its output to Hi-Z, allowing

VRLC/VBIAS to be externally driven.

RLCDACRNG

Sets the output range of the RLCDAC.

0 = RLCDAC ranges from 0 to AVDD (approximately),

1 = RLCDAC ranges from 0 to VRT (approximately).

Sets the output latency in ADC clock periods.

1 ADC clock period = 2 MCLK periods except in Mode 3 where 1 ADC

clock period = 3 MCLK periods.

Setup

7:6

DEL[1:0]

00 = Minimum latency

01 = Delay by one ADC clock

period

10 = Delay by two ADC clock periods

11 = Delay by three ADC clock

periods

3:0

RLCV[3:0]

1111

Controls RLCDAC driving VRLC pin to define single ended signal

reference voltage or Reset Level Clamp voltage. See Electrical

Characteristics section for ranges.

CDS mode reset timing adjust.

5:4

CDSREF[1:0]

00 = Advance 1 MCLK period

01 = Normal

10 = Retard 1 MCLK period

11 = Retard 2 MCLK periods

Monochrome mode channel select.

Setup

7:6

CHAN[1:0]

00 = Red channel select

01 = Green channel select

10 = Blue channel select

11 = Reserved

Software

Reset

Any write to Software Reset causes all cells to be reset.

Auto-cycle

Reset

Any write to Auto-cycle Reset causes the auto-cycle counter to reset

to RINP.

LINEBYLINE

Selects line by line operation 0 = normal operation,

1 = line by line operation.

When line by line operation is selected MONO is forced to 1 and

CHAN[1:0] to 00 internally, ensuring that the correct internal timing signals

are produced. Green and Blue PGAs are also disabled to save power.

ACYCNRLC

When LINEBYLINE = 0 this bit has no effect.

When LINEBYLINE = 1 this bit determines the function of the RLC/ACYC

input pin and the input multiplexer and offset/gain register controls.

0 = RLC/ACYC pin enabled for Reset Level Clamp. Internal selection of

input and gain/offset multiplexers,

1 = Auto-cycling enabled by pulsing the RLC/ACYC input pin.

See Table 4, Colour Selection Description in Line-by-Line Mode for colour

selection mode details.

When auto-cycling is enabled, the RLC/ACYC pin cannot be used for

reset level clamping. The RLCINT bit may be used instead.

2FME

When LINEBYLINE = 0 this bit has no effect.

When LINEBYLINE = 1 this bit controls the input force mux mode:

0 = No force mux, 1 = Force mux mode. Forces the input mux to be

selected by FM[1:0] separately from gain and offset multiplexers.

See Table 4 for details.

3RLCINT

When LINEBYLINE = 1 and ACYCNRLC = 1 this bit is used to determine

whether Reset Level Clamping is used.

0 = RLC disabled, 1 = RLC enabled.

5:4

INTM[1:0]

Colour selection bits used in internal modes.

00 = Red, 01 = Green, 10 = Blue and 11 = Reserved.

See Table 4 for details.

Setup

7:6

FM[1:0]

Colour selection bits used in input force mux modes.

00 = Red, 01 = Green, 10 = Blue and 11 = Reserved.

See Table 4 for details.

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