X24640PI datasheet(5/17 Pages) XICOR

5 / 17 page

X24640

Figure 4. Device Addressing

R/ W

DEVICE

SELECT

S 2

DEVICE TYPE

IDENTIFIER

SLAVE ADDRESS BYTE

DATA BYTE

LOW ORDER WORD ADDRESS

WORD ADDRESS BYTE 0

A10

HIGH ORDER WORD ADDRESS

A11

X24640 WORD ADDRESS BYTE 1

A12

7038 FM 06

DEVICE ADDRESSING

Following a start condition, the master must output the

address of the slave it is accessing. The ﬁrst four bits

of the Slave Address Byte are the device type identiﬁer

bits. These must equal “1010”. The next 3 bits are the

device select bits S0, S1, and S2. This allows up to 8

devices to share a single bus. These bits are

compared to the S0, S1, and S2 device select input

pins. The last bit of the Slave Address Byte deﬁnes the

operation to be performed. When the R/W bit is a one,

then a read operation is selected. When it is zero then

a write operation is selected. Refer to ﬁgure 4. After

loading the Slave Address Byte from the SDA bus, the

device compares the device type bits with the value

“1010” and the device select bits with the status of the

device select input pins. If the compare is not successful,

no acknowledge is output during the ninth clock cycle

and the device returns to the standby mode.

The word address is either supplied by the master or

obtained from an internal counter, depending on the

operation. The master must supply the two Word

Address Bytes as shown in ﬁgure 4.

The internal organization of the E2 array is 256 pages by

32 bytes per page. The page address is partially

contained in the Word Address Byte 1 and partially in

bits 7 through 5 of the Word Address Byte 0. The byte

address is contained in bits 4 through 0 of the Word

Address Byte 0. See ﬁgure 4.

X24640PI Scheda tecnica(PDF) 5 Page - Xicor Inc.

X24640PI Scheda tecnica(HTML) 5 Page - Xicor Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Scheda tecnica Scarica

Link URL