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CS49325 Scheda tecnica(PDF) 21 Page - Cirrus Logic

Il numero della parte CS49325
Spiegazioni elettronici  Multi-Standard Audio Decoder Family
PDF  90 Pages
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Produttore elettronici  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS49325 Scheda tecnica(HTML) 21 Page - Cirrus Logic

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CS49300 Family DSP
DS339F7
21
1.14. Switching Characteristics — Parallel Data Input
(VA, VD[3:1] = 2.5 V
±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)
Notes: 1. CMPREQ signal is asynchronous to CLKIN and can change at any time relative to CLKIN.
2. Certain timing parameters are normalized to the DSP clock, DCLK, in nanoseconds. The DSP clock can
be defined as follows:
External CLKIN Mode:
DCLK == CLKIN/4 before and during boot
DCLK == CLKIN after boot
Internal Clock Mode:
DCLK == 10MHz before and during boot, i.e. DCLK == 100ns
DCLK == 65 MHz after boot, i.e. DCLK == 15.4ns
It should be noted that DCLK for the internal clock mode is application specific. The application code
users guide should be checked to confirm DCLK for the particular application.
Parameter
Symbol
Min
Max
Unit
CMPCLK Period
Tcmpclk
4*DCLK + 10
-
ns
DATA[7:0] setup before CMPCLK high
Tcmpsu
10
-
ns
DATA[7:0] hold after CMPCLK high
Tcmphld
10
-
ns
Delay from falling edge of CMPREQ to CMPCLK rising edge
Treqclk
0-
ns
Tcmpsu
Tcmpclk
Tcmphld
CMPREQ
CMPCLK
DATA[7:0]
Treqclk
Figure 11. Parallel Data Timing (when not in a parallel control mode)



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