GTL2010BS datasheet(5/20 Pages) NXP

5 / 20 page

GTL2010_6

Product data sheet

Rev. 06 — 3 March 2008

5 of 20

NXP Semiconductors

GTL2010

10-bit bidirectional low voltage translator

Application design-in information

8.1 Bidirectional translation

For the bidirectional clamping conﬁguration, higher voltage to lower voltage or lower

voltage to higher voltage, the GREF input must be connected to DREF and both pins

pulled to HIGH side VCC through a pull-up resistor (typically 200 kΩ). A ﬁlter capacitor on

DREF is recommended. The processor output can be totem pole or open-drain (pull-up

resistors may be required) and the chip set output can be totem pole or open-drain

(pull-up resistors are required to pull the Dn outputs to VCC). However, if either output is

totem pole, data must be unidirectional or the outputs must be 3-stateable and the outputs

must be controlled by some direction control mechanism to prevent HIGH-to-LOW

contentions in either direction. If both outputs are open-drain, no direction control is

needed. The opposite side of the reference transistor (SREF) is connected to the

processor core power supply voltage. When DREF is connected through a 200 k

Ω resistor

to a 3.3 V to 5.5 V VCC supply and SREF is set between 1.0 V to (VCC − 1.5 V), the output

of each Sn has a maximum output voltage equal to SREF and the output of each Dn has

a maximum output voltage equal to VCC.

Typical bidirectional voltage translation.

Fig 4.

Bidirectional translation to multiple higher voltage levels such as an I2C-bus

application

GREF

DREF

002aac060

200 k

Ω

CHIPSET I/O

VCC

5 V

totem pole or

open-drain I/O

GND

SREF

increase bit size

by using 10-bit GTL2010

or 22-bit GTL2000

CHIPSET I/O

VCC

3.3 V

CPU I/O

VCORE

1.8 V

1.5 V

1.2 V

1.0 V

GTL2010BS Scheda tecnica(PDF) 5 Page - NXP Semiconductors

GTL2010BS Scheda tecnica(HTML) 5 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Scheda tecnica Scarica

Link URL