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P89LPC985 Scheda tecnica(PDF) 59 Page - NXP Semiconductors |
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P89LPC985 Scheda tecnica(HTML) 59 Page - NXP Semiconductors |
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59 / 85 page ![]() P89LPC980_982_983_985_2 © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 8 February 2010 59 of 85 NXP Semiconductors P89LPC980/982/983/985 8-bit microcontroller with accelerated two-clock 80C51 core The ADC consists of an 8-input multiplexer which feeds a sample-and-hold circuit providing an input signal to comparator inputs. The control logic in combination with the SAR drives a digital-to-analog converter which provides the other input to the comparator. The output of the comparator is fed to the SAR. 8.2 Features 10-bit, 8-channel multiplexed input, successive approximation ADCs. (10-bit, 4-channel on P89LPC983) Eight result register pairs. Six operating modes: Fixed channel, single conversion mode. Fixed channel, continuous conversion mode. Auto scan, single conversion mode. Auto scan, continuous conversion mode. Dual channel, continuous conversion mode. Single step mode. Three conversion start modes: Timer triggered start. Start immediately. Edge triggered. 10-bit conversion time of 4 μs at an A/D clock of 9.0 MHz. Interrupt or polled operation. Boundary limits interrupt. Clock divider. Power-down mode. |
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