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PBLS4002D Scheda tecnica(PDF) 3 Page - NXP Semiconductors |
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PBLS4002D Scheda tecnica(HTML) 3 Page - NXP Semiconductors |
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3 / 15 page ![]() PBLS4002D_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 5 January 2009 3 of 15 NXP Semiconductors PBLS4002D 40 V PNP BISS loadswitch [1] Device mounted on an FR4 (PCB), single-sided copper, tin-plated and standard footprint. [2] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm2. [3] Device mounted on a ceramic PCB, Al2O3, standard footprint. Ptot total power dissipation Tamb ≤ 25 °C [1] - 250 mW [2] - 350 mW [3] - 400 mW TR2; NPN resistor-equipped transistor VCBO collector-base voltage open emitter - 50 V VCEO collector-emitter voltage open base - 50 V VEBO emitter-base voltage open collector - 10 V VI input voltage positive - +30 V negative - −10 V IO output current - 100 mA ICM peak collector current single pulse; tp ≤ 1 ms - 100 mA Ptot total power dissipation Tamb ≤ 25 °C - 200 mW Per device Ptot total power dissipation [1] - 400 mW [2] - 530 mW [3] - 600 mW Tj junction temperature - 150 °C Tamb ambient temperature −65 +150 °C Tstg storage temperature −65 +150 °C Table 5. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit |
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