SC16C751B_2

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 02 — 10 October 2008

23 of 32

NXP Semiconductors

SC16C751B

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

[1]

Applies to external clock, crystal oscillator max 24 MHz.

[2]

RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.

[3]

Reset pulse must happen when these signals are inactive: CS, IOR, IOW.

10.1 Timing diagrams

Fig 5.

General read timing

002aad015

A0 to A2

IOR

D0 to D7

valid

address

valid

address

active

active

active

data

CS

Fig 6.

General write timing

002aad014

A0 to A2

IOW

D0 to D7

data

active

active

active

CS

valid

address

valid

address