EM351-RTR datasheet(35/240 Pages) ETC2

35 / 240 page

EM351 / EM357

5-8

120-035X-000D

Preliminary

identification of the peripheral is captured for later debugging. Note that only peripherals capable of writing

data to RAM, such as received packet data or a received serial port character, can generate this interrupt.

5.2.3

Registers

Appendix A, Register Address Table provides a short description of all application-accessible registers within

the EM35x. Complete descriptions are provided at the end of each applicable peripheral’s description. The

registers are mapped to the system address space starting at address 0x40000000. These registers allow for

the control and configuration of the various peripherals and modules. The CPU only performs word-aligned

accesses on the system bus. The CPU performs a word aligned read-modify-write for all byte, half-word, and

unaligned writes and a word-aligned read for all reads. Ember recommends accessing all peripheral registers

using word-aligned addressing.

As with the RAM, the peripheral registers fall within an address range that allows for bit-band access by the

ARM

® CortexTM-M3, but the standard MPU configuration does not allow access to this alias address range.

5.3

Memory Protection Unit

The EM35x includes the ARM

® CortexTM-M3 Memory Protection Unit, or MPU. The MPU controls access rights

and characteristics of up to eight address regions, each of which may be divided into eight equal sub-regions.

Refer to the ARM® CortexTM-M3 Technical Reference Manual (DDI 0337A) for a detailed description of the MPU.

Ember software configures the MPU in a standard configuration and application software should not modify it.

The configuration is designed for optimal detection of illegal instruction or data accesses. If an illegal access

is attempted, the MPU captures information about the access type, the address being accessed, and the

location of the offending software. This simplifies software debugging and increases the reliability of deployed

devices. As a consequence of this MPU configuration, accessing RAM and register bit-band address alias regions

is not permitted, and generates a bus fault if attempted.

EM351-RTR Scheda tecnica(PDF) 35 Page - List of Unclassifed Manufacturers