MPC8308 datasheet(12/88 Pages) FREESCALE

Il numero della parte	MPC8308

Spiegazioni elettronici	MPC8308 PowerQUICC II Pro Processor Hardware Specification

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MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor

DDR2 SDRAM

Figure 4 illustrates the DDR2 input timing diagram showing the tDISKEW timing parameter.

Figure 4. Timing Diagram for tDISKEW

6.2.2

DDR2 SDRAM Output AC Timing Specifications

Table 18. DDR2 SDRAM Output AC Timing Specifications

Parameter

Symbol 1

Min

Max

Unit

Notes

MCK[n] cycle time, MCK[n]/MCK[n] crossing

tMCK

7.5

ADDR/CMD output setup with respect to MCK

tDDKHAS

266 MHz

2.9

—

ADDR/CMD output hold with respect to MCK

tDDKHAX

266 MHz

2.33

—

MCS[n] output setup with respect to MCK

tDDKHCS

266 MHz

3.15

—

MCS[n] output hold with respect to MCK

tDDKHCX

266 MHz

3.15

—

MCK to MDQS Skew

tDDKHMH

–0.6

0.6

MDQ//MDM/MECC output setup with respect to

MDQS

tDDKHDS,

tDDKLDS

266 MHz

900

—

MDQ//MDM/MECC output hold with respect to

MDQS

tDDKHDX,

tDDKLDX

266 MHz

1100

—

MCK[n]

tMCK

MDQ[x]/

MDQS[n]

tDISKEW

MECC[x]

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