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DSP56824 Scheda tecnica(PDF) 8 Page - Freescale Semiconductor, Inc |
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DSP56824 Scheda tecnica(HTML) 8 Page - Freescale Semiconductor, Inc |
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8 / 62 page ![]() 8 DSP56824 Technical Data Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the DSP56824 are organized into functional groups, as shown in Table 3 and as illustrated in Figure 2. In Table 4 through Table 16, each table row describes the signal or signals present on a pin. Figure 2 provides a diagram of DSP56824 signals by functional group. Table 3. Functional Group Pin Allocations Functional Group Number of Pins Detailed Description Power (VDD or VDDPLL) 10 Table 4 Ground (VSS or VSSPLL) 10 Table 5 PLL and Clock 4 Table 6 Address Bus 16 Table 7 Data Bus 16 Table 8 Bus Control 4 Table 9 Interrupt and Mode Control 3 Table 10 Programmable Interrupt General Purpose Input/Output 8 Table 11 Dedicated General Purpose Input/Output 8 Table 12 Serial Peripheral Interface (SPI) Ports1 1. Alternately, GPIO pins 8 Table 13 Synchronous Serial Interface (SSI) Port1 6 Table 14 Timer Module1 2 Table 15 JTAG/On-Chip Emulation (OnCE) 5 Table 16 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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