TMS320DM647 datasheet(5/181 Pages) TI

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TMS320DM647

TMS320DM648

www.ti.com

SPRS372F – JANUARY 2010 – REVISED SEPTEMBER 2009

6.2

Recommended Clock and Control Signal Transition

Features

................................................... 1

Behavior

............................................ 59

1.1

Trademarks

.......................................... 2

6.3

Power Supplies

..................................... 59

1.2

Description

........................................... 2

6.4

PLL1 Controller

..................................... 65

1.3

Functional Block Diagram

............................ 4

6.5

PLL2 Controller

..................................... 69

Revision History

.............................................. 6

6.6

Enhanced Direct Memory Access (EDMA3)

Controller

........................................... 71

Device Overview

........................................ 7

6.7

Reset Controller

.................................... 84

2.1

Device Characteristics

............................... 7

6.8

Interrupts

............................................ 89

2.2

CPU (DSP Core) Description

........................ 8

6.9

DDR2 Memory Controller

........................... 93

2.3

C64x+ CPU

......................................... 11

6.10

External Memory Interface A (EMIFA)

............ 104

2.4

Memory Map Summary

............................. 12

6.11

Video Port

......................................... 111

2.5

Pin Assignments

.................................... 16

6.12

VCXO Interpolated Control (VIC)

................. 119

2.6

Terminal Functions

................................. 20

6.13

Universal Asynchronous Receiver/Transmitter

2.7

Device Support

..................................... 34

(UART)

............................................ 121

Device Configuration

................................. 38

6.14

Serial Peripheral Interface Port (SPI)

............. 123

6.15

Inter-Integrated Circuit (I2C)

...................... 127

3.1

System Module Registers

.......................... 38

6.16

Host-Port Interface (HPI) Peripheral

.............. 131

3.2

Bootmode Registers

................................ 39

6.17

Peripheral Component Interconnect (PCI)

........ 142

3.3

Pullup/Pulldown Resistors

.......................... 49

6.18

Multichannel Audio Serial Port (McASP)

.......... 147

System Interconnect

.................................. 50

6.19

3-Port Ethernet Switch Subsystem (3PSW)

....... 155

4.1

Internal Buses, Bridges, and Switch Fabrics

....... 50

6.20

Management Data Input/Output (MDIO)

.......... 165

4.2

Data Switch Fabric Connections

................... 50

6.21

Timers

............................................. 166

4.3

Configuration Switch Fabric

........................ 52

6.22

VLYNQ Peripheral

................................. 168

Device Operating Conditions

....................... 54

6.23

General-Purpose Input/Output (GPIO)

............ 171

5.1

Absolute Maximum Ratings

........................ 54

6.24

Emulation Features and Capability

............... 173

6.25

IEEE 1149.1 JTAG

................................ 174

5.2

Recommended Operating Conditions

.............. 55

Mechanical Data

...................................... 176

5.3

Electrical Characteristics

........................... 56

7.1

Thermal Data for ZUT

............................. 176

Peripheral Information and Electrical

Specifications

.......................................... 57

7.2

Packaging Information

............................ 177

6.1

Parameter Information

.............................. 57

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