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TUSB1310 Scheda tecnica(PDF) 25 Page - Texas Instruments |
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TUSB1310 Scheda tecnica(HTML) 25 Page - Texas Instruments |
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25 / 36 page ![]() CEXTSS CEXT 4 .7nF VSSA VSSA 4.7 nF R1EXT R1EXTRTN 10KW ± 1 % VBUS DP DM USB Connector XI VSSOSC XO Crystal Connection ULPI PIPE RX PIPE TX Link Controller JTAG JTAG 10KW ± 1% 90.9KW ± 1 % TUSB1310 www.ti.com SLLSE16C – DECEMBER 2009 – REVISED AUGUST 2010 5 DESIGN GUIDELINES 5.1 Chip Connection on PCB Components should be placed close to the TUSB1310 to reduce the trace length of the interface between the components and the TUSB1310. If external capacitors can not accommodate a close placement, shielding to ground is recommended. Figure 5-1. Analog Pin Connections 5.1.1 USB Connector Pins Connection Differential pair signals, DP/DM, SSTXP/SSTXN, SSRXP/SSRXN, should be kept as short as possible. The differential pair traces should be trace-length matched and parallelism should be maintained. They also need to minimize vias and corners and should avoid crossing plane splits and stubs. Figure 5-2 and Figure 5-3 are for visual reference only. Copyright © 2009–2010, Texas Instruments Incorporated DESIGN GUIDELINES 25 Submit Documentation Feedback Product Folder Link(s): TUSB1310 |
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