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FS403 Scheda tecnica(PDF) 75 Page - List of Unclassifed Manufacturers

Il numero della parte FS403
Spiegazioni elettronici  PC to TV Video Scan Converters
PDF  104 Pages
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Produttore elettronici  ETC2 [List of Unclassifed Manufacturers]
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FS403 Scheda tecnica(HTML) 75 Page - List of Unclassifed Manufacturers

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FS401, FS403
PRODUCT SPECIFICATION
REV. NO. 1.7
75
JANUARY 24, 2007
COPYRIGHT
© 1999 FOCUS ENHANCEMENTS, INC.
5. Functional Description
8 Bit
ADC
Gain
RGB/YUV
Matrix
9 Bit
DAC
Vertical
Scaler
External
Sync
DRAM
Memory
Video
Encoder
YUV/RGB
Matrix
8 Bit
ADC
8 Bit
ADC
9 Bit
DAC
9 Bit
DAC
Horizontal
Scaler
Clamp
VGA
PLL
DRAM
PLL
Serial Bus
Interface
RED
GRN
BLU
LUMA_R_V
CVBS_G_Y
CHROMA_B_U
VGA_HSYNC
VGA_VSYNC
Xtal_N
Xtal_P
/3
FLP_RST
R_DIG
G_DIG
B_DIG
Embedded
Processor
VSYNC
HSYNC
CSYNC
Built In
Pattern
ADC_SEL
OSD Overlay
Figure 5. Functional Block Diagram
(RGB7-0 and A/D_SEL\ omitted on FS401)
Details of how to connect and setup the FS400 are included in this section. Overall design principles are
in the Architectural Overview section. Operation of the FS400 is divided into four sections:
•
Capture Engine
•
Frame Store Controller
•
Encoder Engine
•
Serial Control Port
•
Embedded Microprocessor
5.1 Capture Engine
A/D Converters, Built In Pattern Generator, RGB/YUV Matrix, Vertical Scaler and Flicker Filter comprise
the Capture Engine.
5.1.1 Timing and Control
Timing of the Capture Engine is derived from the Input Control Block which contains a series of counters
and decoders synchronized to the A/D sample clock, ADCK. ADCK is derived from a phase locked loop
referenced to the leading edge of horizontal sync.
Sync polarity is auto-detected by sensing the leading edge of horizontal sync HS_IN and vertical sync,
VS_IN. This edge is the reference for the phase-locked loop tracking the horizontal pixel count and the
vertical line counter.
Registers that interface with the Capture Timing and Control block are:
1.
IHS
4.
SHV (read only)
7.
EVV (read only)



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