SC403EVB datasheet(19/32 Pages) SEMTECH

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SC403

Time

IPEAK

ILOAD

ILIM

Figure 7 — Valley Current Limit

Setting the valley current limit to 6A results in a peak induc-

tor current of 6A plus the peak-to-peak ripple current. In

this situation, the average (load) current through the induc-

tor is 6A plus one-half the peak-to-peak ripple current.

The internal 10μA current source is temperature compen-

sated at 4100ppm in order to provide tracking with the

RDS

ON.

The

ILIM value is calculated by the following equation.

ILIM = 1176 x ILIM x [0.088 x (5V - VDD) + 1] (Ω)

where I

LIM is in Amps.

When selecting a value for R

ILIM do not exceed the absolute

maximum voltage value for the ILIM pin. Note that because

the low-side MOSFET with low RDS

ON is used for current

sensing, the PCB layout, solder connections, and PCB connec-

tion to the LX node must be done carefully to obtain good

results. R

ILIM should be connected directly to LXS (pin 28).

Soft-Start of PWM Regulator

SC403 has a programmable soft-start time that is con-

trolled by an external capacitor at the SS pin. After the

controller meets both UVLO and EN/PSV thresholds, the

controller has an internal current source of 2.75µA flowing

through the SS pin to charge the capacitor. During the

start up process (Figure 8), 50% of the voltage at the SS

pin is used as the reference for the FB comparator. The

PWM comparator issues an on-time pulse when the

voltage at the FB pin is less than 50% of the SS pin. As

result, the output voltage follows the SS start voltage. The

output voltage reaches and maintains regulation when

the soft start voltage is > 1.5V. The time between the first

LX pulse and when V

OUT meets regulation is the soft start

time (t

SS). The calculation for the soft-start time is shown

by the following equation.

The voltage at the SS pin continues to ramp up and eventu-

ally is equal to 64% of V

DD. After soft start completes, the FB

pin voltage is compared to an internal reference of 0.75V.

The delay time between the V

OUT regulation point and

PGOOD going high is shown by the following equation.

DELAY

PGOOD

Time (400µs/div)

(10mV/div)

(2V/div)

(5V/div)

(500mV/div)

Figure 8 — Soft-start Timing Diagram

Pre-Bias Startup

SC403 can start up as if in a soft-start condition with an

existing output voltage level. The soft start time is still the

same as normal start up (when the output voltage starts

from zero). The output voltage starts to ramp up when

one-half of the voltage at SS pin meets the pre-charge FB

voltage level. Pre-bias startup is achieved by turning off

the lower gate when the inductor current falls below zero.

This method prevents the output voltage from

decreasing.

Power Good Output

The PGOOD (power good) output is an open-drain output

which requires a pull-up resistor. When the voltage at the

FB pin is 10% below the nominal voltage, PGOOD is pulled

low. It is held low until the output voltage returns above

92% of nominal.

PGOOD will transition low if the V

FB pin exceeds +20% of

nominal, which is also the over-voltage shutdown thresh-

old. PGOOD also pulls low if the EN/PSV pin is low when

DD voltage is present.

Applications Information (continued)

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