SA8806A

sames

7/10

The data in memory is constantly being displayed on the liquid crystal display. New

data is displayed as soon as it is latched into memory.

When a high level (+5V) on a backplane driver output corresponds with a low level

(0V) on a segment driver output (or vice versa), the LCD segment to which they are

connected, will be activated (see Diagram 3).

The backplane multiplex rate is determined by the clock frequency on the CLK input.

Diagram 3: LCD Driving Signals