SA9203/5

sames

10/14

INT

This active high output (default after reset) operates as follows:

When disabled (via A6), INT remains reset. On either the rising or trailing edge of STB

(programmable via D6 of Port B-F direction control register), INT is set. INT remains

set until Port A (or any bit of PORT A if in bit- addressing mode) is read by the

microprocessor at which point INT is reset, remaining so until the next active edge of

STB. (See figure 14 for timing diagram). The output polarity of INT is programmed via

D7 of the Port B- F dirction control register (See Figure 11).

RST

This active low reset signal resets the contents of all registers to zero. Sets all ports to

input mode and the bi-directional data/address bus to input. A valid RST signal is

specified as an active low pulse of 100ns minimum duration.

CS

The active low CS signal is internally latched by the trailing edge of ALE.

TIMING DIAGRAMS

FIGURE 12: µP Read Waveforms

RDE

t

t

t

RD

DR-01270

LL

LC

t

ALE

CS

AD -8/A

AL

t

08

LA

t

AD

t

ADDRESS

RDF

t

t RD

t CC

LD

RV

t

CL

t

DATA VALID