4

FN6981.1

November 19, 2009

CP2[C,B,A]

39, 40, 41

Control pins for setting equalizer 2. CMOS logic inputs. Pins are read as a 3-digit number to set

the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ

resistor.

CP1[C,B,A]

42, 43, 44

Control pins for setting equalizer 1. CMOS logic inputs. Pins are read as a 3-digit number to set

the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ

resistor.

ENB

45

Serial data enable (active low), CMOS logic. Internal registers can be programmed with DI and

CLK pins only when the ENB pin is ‘LOW’. Internally pulled down.

CLK

46

Serial data clock, CMOS logic. Synchronous clock for serial data on DI and DO pins. Data on DI

is latched on the rising clock edge. Clock speed is recommended to be between 10MHz and

20MHz. Internally pulled down.

EXPOSED

PAD

-

Exposed ground pad. For proper electrical and thermal performance, this pad should be

connected to the PCB ground plane.

Pin Descriptions

PIN NAME

PIN NUMBER

DESCRIPTION

QLx4600-SL30