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MB90F482B Scheda tecnica(PDF) 34 Page - fujitsu semiconductor |
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MB90F482B Scheda tecnica(HTML) 34 Page - fujitsu semiconductor |
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34 / 124 page ![]() MB90480B/485B Series 34 DS07-13722-11E (2) Port Direction Registers *1 : The value is set to “ ⎯” on MB90485B series only. *2 : The initial value of this bit is “XX000000B” on MB90485B series only. • When a set of pins is functioning as a port, the corresponding signal pins are controlled as follows. 0 : Input mode. 1 : Output mode. Reset to “0”. Notes : • When any of these registers are accessed using a read-modify-write type instruction (such as a bit set instruction) , the bit specified in the instruction will be set to the indicated value. However, the contents of output registers corresponding to any other bits having input settings will be rewritten to the input values of those pins at that time. For this reason, when changing any pin that has been used for input to output, first write the desired value to the PDR register before setting the DDR register for output. • P76, P77 (MB90485B series only) This port has no DDR. To use P77 and P76 as I2C pins, set the PDR value to “1” so that port data remains enabled (to use P77 and P76 for general purposes, disable I2C) . The port is an open drain output (with no P-ch) . To use it as an input port, therefore, set the PDR to “1” to turn off the output transistor and add a pull-up resistor to the external output. DDR0 Initial value Access Address : 000010H 00000000B R/W DDR1 Address : 000011H 00000000B R/W DDR2 Address : 000012H 00000000B R/W DDR3 Address : 000013H 00000000B R/W DDR4 Address : 000014H 00000000B R/W DDR5 Address : 000015H 00000000B R/W DDR6 Address : 000016H 00000000B R/W DDR7 Address : 000017H 00000000B*2 R/W DDR8 Address : 000018H 00000000B R/W DDR9 Address : 000019H 00000000B R/W DDRA Address : 00001AH ----0000B R/W 76 5 4 3 2 1 0 D06 D07 D05 D04 D03 D02 D01 D00 D16 D17 D15 D14 D13 D12 D11 D10 76 5 4 3 2 1 0 76 5 4 3 2 1 0 D26 D27 D25 D24 D23 D22 D21 D20 76 5 4 3 2 1 0 D36 D37 D35 D34 D33 D32 D31 D30 76 5 4 3 2 1 0 D46 D47 D45 D44 D43 D42 D41 D40 76 5 4 3 2 1 0 D56 D57 D55 D54 D53 D52 D51 D50 76 5 4 3 2 1 0 D66 D67 D65 D64 D63 D62 D61 D60 76 5 4 3 2 1 0 D75 D74 D73 D72 D71 D70 D77*1 D76*1 76 5 4 3 2 1 0 D86 D87 D85 D84 D83 D82 D81 D80 76 5 4 3 2 1 0 D96 D97 D95 D94 D93 D92 D91 D90 76 5 4 3 2 1 0 ⎯ ⎯⎯ ⎯ DA3 DA2 DA1 DA0 |
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