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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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MB90F482B Scheda tecnica(PDF) 107 Page - fujitsu semiconductor |
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MB90F482B Scheda tecnica(HTML) 107 Page - fujitsu semiconductor |
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107 / 124 page  MB90480B/485B Series DS07-13722-11E 107 (14) Trigger Input Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = − 40 °C to + 85 °C) * : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”. (15) Up-down Counter Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = − 40 °C to + 85 °C) * : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”. Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tTRGH tTRGL ADTG, IRQ0 to IRQ7 ⎯ 5 tCP* ⎯ ns Normal operation 1 ⎯μs Stop mode Parameter Symbol Pin name Conditions Value Unit Min Max AIN input “H” pulse width tAHL AIN0, AIN1, BIN0, BIN1 Load conditions 80 pF 8 tCP* ⎯ ns AIN input “L” pulse width tALL 8 tCP* ⎯ ns BIN input “H” pulse width tBHL 8 tCP* ⎯ ns BIN input “L” pulse width tBLL 8 tCP* ⎯ ns AIN ↑→ BIN↑ time tAUBU 4 tCP* ⎯ ns BIN ↑→ AIN↓ time tBUAD 4 tCP* ⎯ ns AIN ↓→ BIN↑ time tADBD 4 tCP* ⎯ ns BIN ↓→ AIN↑ time tBDAU 4 tCP* ⎯ ns BIN ↑→ AIN↑ time tBUAU 4 tCP* ⎯ ns AIN ↑→ BIN↓ time tAUBD 4 tCP* ⎯ ns BIN ↓→ AIN↑ time tBDAD 4 tCP* ⎯ ns AIN ↓→ BIN↑ time tADBU 4 tCP* ⎯ ns ZIN input “H” pulse width tZHL ZIN0, ZIN1 4 tCP* ⎯ ns ZIN input “L” pulse width tZLL 4 tCP* ⎯ ns 0.8 VCC IRQ0 to IRQ7 ADTG 0.8 VCC 0.2 VCC 0.2 VCC tTRGH tTRGL |
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