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Z550 Scheda tecnica(PDF) 21 Page - Intel Corporation |
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Z550 Scheda tecnica(HTML) 21 Page - Intel Corporation |
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21 / 73 page ![]() Low Power Features Datasheet 21 Figure 5 shows the relative exit latencies of the package sleep states discussed above. Note: Figure 5 uses pre-silicon estimates. Silicon based data will be provided in a future revision of this document. Figure 5. Exit Latency Table Latency (µs) C0 (HFM) C0 (LFM) C1 Both threads halted Most clocks off C1E C1 plus frequency and VID at LFM C2 Similar to C1 but Intel® SCH blocks interrupts C4 C2 plus PLLs off; VID = cache retention Vcc Some L2 cache off C6 C2 plus PLLs off; VID = C6 powerdown Vcc L2 cache off 0 0.1 1 10 100 0 TDP |
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