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C5NPD0-DS Scheda tecnica(PDF) 73 Page - Freescale Semiconductor, Inc |
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C5NPD0-DS Scheda tecnica(HTML) 73 Page - Freescale Semiconductor, Inc |
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73 / 100 page  AC Timing Specifications 73 V 04 See Figure 11. Output timing specifications for LVTTL pins are given with a 10pF load on the output. Other loads can be simulated with the IBIS model available from C-Port. The LVPECL driver is specified into a 50 Ω load terminated to a (VDD33 - 2V) reference. Figure 11 Test Loading Conditions Clock Timing Specifications The system clock timing is shown in Figure 12 and described in Table 39. Figure 12 System Clock Timing Diagram +2V LVTTL LVPECL DUT DUT 10pF 50 Ω VDD33 Tsc Tsh SCLK Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 SCLKX CCLKn TccN Tsl Tcch Tccl Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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