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M41ST87YSS6F Scheda tecnica(PDF) 25 Page - STMicroelectronics |
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M41ST87YSS6F Scheda tecnica(HTML) 25 Page - STMicroelectronics |
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25 / 52 page ![]() M41ST87Y, M41ST87W Operating modes Doc ID 9497 Rev 8 25/52 Table 5. Tamper detect timing Figure 20. RAM clear hardware hookup (SOX28 MX package only) 1. Most inverting charge pumps drive OUT to ground when device shut down is enabled (SHDN = logic low). Therefore, an n- channel enhancement mode MOSFET should be used to isolate the OUT pin from the VOUT of the M41ST87. 2. In order to avoid turning on an on-chip parasitic diode when driving VOUT negative, a p-channel enhancement mode MOSFET should be used to isolate the VOUT pin from the negative voltage generated by the inverting charge pump. Symbol Parameter CLRPW 1 CLRPW 0 Min Typ Max Unit tCLRD (1) 1. With input capacitance = 70 pF and resistance = 50 Ω. Tamper RAM clear ext delay X X 1.0(2) 2. If the OF bit is set, tCLRD(min) = 0.5 ms. 1.5 2.0 ms tCLR Tamper clear timing 00 1 s 01 4 s 10 8 s 11 16 s AI07804 VCC PFO1 EX SCL M41ST87Y/W WDI RSTIN1 RSTIN2 PFI1 PFI2 VSS VBAT F32k IRQ/OUT SQW/FT RST VOUT ECON SDA CAP+ CAP– Inverting Charge Pump SHDN OUT IN TP1IN TPCLR TP2IN Pushbutton Reset PFO2 Low-Power SRAM VCC Negative Output (–1 x VIN) E To RST To LED Display (2) (1) To NMI To INT To 32kHz Inhibit 5V Regulator VCC VIN |
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