XC161CS-32F_06 datasheet(21/87 Pages) INFINEON

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XC161CS-32F

Derivatives

Functional Description

Data Sheet

V1.2, 2006-08

Functional Description

The architecture of the XC161 combines advantages of RISC, CISC, and DSP

processors with an advanced peripheral subsystem in a very well-balanced way. In

addition, the on-chip memory blocks allow the design of compact systems-on-silicon with

maximum performance (computing, control, communication).

The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data

SRAM) and the set of generic peripherals are connected to the CPU via separate buses.

Another bus, the LXBus, connects additional on-chip resources as well as external

resources (see Figure 3).

This bus structure enhances the overall system performance by enabling the concurrent

operation of several subsystems of the XC161.

The following block diagram gives an overview of the different on-chip components and

of the advanced, high bandwidth internal bus structure of the XC161.

Figure 3

Block Diagram

GPT

C166SV2 - Core

DPRAM

CPU

BRGen BRGen BRGen BRGen

ASC0

USART

ASC1

USART

SSC0

SPI

SSC1

SPI

ADC

8-Bit/

10-Bit

12 Ch

CC1

IIC

BRGen

Twin

CAN

A B

RTC

WDT

Interrupt & PEC

EBC

LXBus Control

External Bus

Control

DSRAM

ProgMem

Flash

256 Kbytes

PSRAM

Osc / PLL

Clock Generator

OCDS

Debug Support

Interrupt Bus

CC2

P 20 P 9 P 7 Port 6

Port 5

Port 4

Port 3

Port 2

PORT1

PORT0

MCB04323_X132

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