IR3502MPBF datasheet(35/39 Pages) IRF

35 / 39 page

IR3502

Page 35 of 39

July 28, 2009

LAYOUT GUIDELINES

The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB

layout, therefore minimizing the noise coupled to the IC.

•

Dedicate at least one middle layer for a ground plane LGND.

•

Connect the ground tab under the control IC to LGND plane through a via.

•

Place VCCL decoupling capacitor VCCL as close as possible to VCCL and LGND pins.

•

Place the following critical components on the same layer as control IC and position them as close as possible

to the respective pins, ROSC, RVDAC, CVDAC, and CSS/DEL. Avoid using any via for the connection.

•

Place the compensation components on the same layer as control IC and position them as close as possible to

EAOUT, FB, VO and VDRP pins. Avoid using any via for the connection.

•

Use Kelvin connections for the remote voltage sense signals, VOSNS+ and VOSNS-, and avoid crossing over

the fast transition nodes, i.e. switching nodes, gate drive signals and bootstrap nodes.

•

Avoid analog control bus signals, VDAC, IIN, and especially EAOUT, crossing over the fast transition nodes.

•

Separate digital bus, CLKOUT, PHSOUT and PHSIN from the analog control bus and other compensation

components.

HOTSET

VCCLDRV

VRRDY

IMON

ENABLE

VOSNS –

Phase ICs

Digital

To VCCL

IIN

VRHOT

VCCL

PHSOUT

CLKOUT

PHSIN

To SYSTEM

VOSNS +

EAOUT

LGND

PLANE

To Thermistor

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