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TLE4470 Scheda tecnica(PDF) 2 Page - Infineon Technologies AG

Il numero della parte TLE4470
Spiegazioni elettronici  Dual Low-Drop Voltage Regulator Very low dropout
PDF  24 Pages
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Produttore elettronici  INFINEON [Infineon Technologies AG]
Homepage  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

TLE4470 Scheda tecnica(HTML) 2 Page - Infineon Technologies AG

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Data Sheet
2
Rev. 1.2, 2008-03-20
TLE 4470
use of an external voltage divider the main output voltage can be set to
V
Q2 ≥ 5 V for the
TLE 4470 G type (PG-DSO-20 package).
V
Q1 is compared to the voltage at pin ADJ2,
which is proportional to the output voltage
V
Q2. A control amplifier drives the base of the
series PNP transistor via a buffer.
The main output voltage
V
Q2 is tracked to the accuracy of the stand-by output.
For the TLE 4470 GS (PG-DSO-14 package) the output voltage is fixed to 5 V.
To save energy e.g. in battery powered body electronic applications, the main regulator
can be switched off via the disable input, which causes the current consumption to drop
to 180
µA typical.
Two additional features of the TLE 4470 are an early warning comparator (can be used
e.g. to monitor the supply voltage
V
I) and reset generator with an adjustable reset delay
time. The TLE 4470 G (PG-DSO-20 package) has in addition an adjustable reset
switching threshold. This feature is useful with microprocessors which guarantee a safe
operation down to voltages below the internally set reset threshold of 4.65 V typical.
Two functions are included in the reset generator, a power-on-reset and an under-
voltage reset. The power-on-reset feature is necessary for a defined start of the
microprocessor when switching on the application. The reset signal is kept low for a
certain delay time after the output voltage
V
Q1 of the regulator has surpassed the reset
threshold. An external delay capacitor sets this delay time. The under voltage reset
circuit supervises the stand-by output voltage. In case
V
Q1 falls below the reset switching
threshold the reset output is set LOW after a short reaction time. The reset LOW signal
is generated down to an output voltage
V
Q1 of 1 V.
Figure 1
Pin Configuration (top view)
GND
GND
10
8
9
7
6
3
5
4
2
120
19
18
17
16
15
14
13
12
11
GND
DIS
D
GND
RQ
SI
AEP02151
SQ
GND
RADJ
GND
GND
ADJ2
GND
Q2
Q2
Q1
Ι
Ι
1
2
GND
7
6
3
5
4
2
114
13
12
11
10
9
8
GND
GND
DIS
SI
AEP02152
GND
D
Ι
GND
GND
RQ
SQ
Q2
Q1
PG-DSO-14
PG-DSO-20



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