PPC8567CVTAUGGA datasheet(127/139 Pages) FREESCALE

127 / 139 page

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

127

Thermal

Millennium Electronics offer different heat sink-to-ambient thermal resistances, that will allow the

MPC8568E to function in various environments.

24.2.1

Recommended Thermal Model

For system thermal modeling, the MPC8568E thermal model without a lid is shown in Figure 70. The

substrate is modeled as a block 33x33x1.18 mm with an in-plane conductivity of 24 W/mK and a

through-plane conductivity of 0.92 W/mK. The solder balls and air are modeled as a single block

33x33x0.58 mm with an in-plane conductivity of 0.034 W/mK and a through plane conductivity of 12.2

W/mK. The die is modeled as 8.2x12.1 mm with a thickness of 0.75 mm. The bump/underfill layer is

modeled as a collapsed thermal resistance between the die and substrate assuming a conductivity of 5.3

W/m•K in the thickness dimension of 0.07 mm. The die is centered on the substrate. The thermal model

uses approximate dimensions to reduce grid. See the case outline for actual dimensions.

Figure 70. MPC8568E Thermal Model

24.2.2

Internal Package Conduction Resistance

For the packaging technology, shown in Table 87, the intrinsic internal conduction thermal resistance paths

are as follows:

•

The die junction-to-case thermal resistance

Heat Source

Substrate

Top View of Model (Not to Scale)

Conductivity

Value

Unit

Die

(8.2

× 12.1 × 0.75mm)

Silicon

Temperature

dependent

W/(m

× K)

Bump/Underfill

(8.2

× 12.1 × 0.75 mm)

Collapsed Resistance

5.3

Substrate

(33

× 33× 1.18 mm)

0.92

Soldera and Air

(33

× 33 × 0.58 mm)

0.034

12.2

substrate

solder/air

die

Bump/Underfill

Side View of Model (Not to scale)

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