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SC28L201 Scheda tecnica(PDF) 79 Page - NXP Semiconductors |
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SC28L201 Scheda tecnica(HTML) 79 Page - NXP Semiconductors |
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79 / 110 page ![]() 9397 750 13138 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 31 October 2005 79 of 110 Philips Semiconductors SC28L201 3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO 8.6.8 Input Change Detect Enable, B (IPCE) IPCE[7:0] bits activate the input change of state detectors. If a pin is configured as an output, the change of state detectors, if enabled, continue to be active and will show a change of state as the I/P port changes. 8.6.9 I/O Port Configuration Registers (I/OPCR0, I/OPCR1, I/OPCR2, I/OPCR3) These four registers contain 4 2-bit fields that set the direction and source for each of the I/O pins associated with the channel. The I/O0B output may be RTSN if MR1[7] is set. It may also signal end of transmission if MR2[5] is set. (Please see the descriptions of these functions under Section 8.2.2 “Mode Register 1 (MR1)” and Section 8.2.3 “Mode Register 2 (MR2)”). The binary settings of the binary 00 combination always configures the I/O pins as ‘inputs’. However, the input circuit of the I/O pins are always active. In actuality, the binary 00 condition only disables the output driver of the pin. Since the input circuit and the associated change-of-state detector is always active, the output signal may generate interrupts or drive counters. This register resets to 0x00 on reset, effectively configuring all I/O pins as inputs. Inputs may be used as RxC, TxC inputs or CTSN and General Purpose Inputs simultaneously. All inputs are equipped with change detectors that may be used to generate interrupts or can be polled, as required. Remark: Both I/O Port A and B default to input upon a hardware reset to avoid hardware conflicts with I/O direction. Table 68: IPCE - Input Change Detect Enable register, A (address 0x32) bit description Bit Symbol Description 7 reserved 6 ∆I/O6B enable. 0 = disable 1 = enable 5 reserved 4 ∆I/O4B enable. 0 = disable 1 = enable 3 ∆I/O3B enable. 0 = disable 1 = enable 2 ∆I/O2B enable. 0 = disable 1 = enable 1 reserved 0 ∆I/O0B enable. 0 = disable 1 = enable |
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