MPL015A2 datasheet(4/8 Pages) FREESCALE

4 / 8 page

MPL015A2

Sensors

Freescale Semiconductor

Pressure

Coefficient Bit-Width Specs

The table below specifies the initial coefficient bit-width specs for the compensation algorithm.

* Factory reserves the option to make these values = 0.

Example Binary Format Definitions:

Sign = 0, Integer Bits = 8, Fractional Bits = 4 :

Coeff = S I7 I6 I5 I4 I3 I2 I1 I0 . F3 F2 F1 F0

Sign = 1, Integer Bits = 4, Fractional Bits = 7 :

Coeff = S I3 I2 I1 I0 . F6 F5 F4 F3 F2 F1 F0

Sign = 0, Integer Bits = 0, Fractional Bits = 6, dec pt zero pad = 2 : Coeff = S 0 . 0 0 F5 F4 F3 F2 F1 F0

Sign = 0, Integer Bits = 0, Fractional Bits = 5, dec pt zero pad = 3 : Coeff = S 0 . 0 0 0 F4 F3 F2 F1 F0

NOTE: Negative coefficients (Sign = 1) are coded in 2’s complement notation.

Coefficient Address Map

For coefficients with less than 16 bits, the lower LSBs are zero. For example, c14 is 14 bits and is stored into 2 bytes as follows:

c14 MS byte = c14[10:3] = [c14b13 , c14b12 , c14b11 , c14b10 , c14b9 , c14b8 , c14b7 , c14b6]

c14 LS byte = c14[2:0] & “00000” = [c14b5 , c14b4 , c14b3 , c14b2 , c14b1 , c14b0 , 0 , 0]

10-bit Output: Compensation Coefficient Specs

Total Coeff.

Bits

c12

Total Bits

Sign Bits

Integer Bits

Fractional Bits

dec pt zero pad

—

Address

Coefficient

$04

a0 MS Byte

$05

a0 LS Byte

$06

b1 MS Byte

$07

b1 LS Byte

$08

b2 MS Byte

$09

b2 LS Byte

$0A

c12 MS Byte

$0B

c12 LS Byte

MPL015A2 Scheda tecnica(PDF) 4 Page - Freescale Semiconductor, Inc

MPL015A2 Scheda tecnica(HTML) 4 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8

Scheda tecnica Scarica

Link URL